1. Field of the Invention
This invention relates generally to the use of interrupts between a plurality of processors. More particularly, it relates to an interrupt technique which provides the capability of a conventional interrupt status register without requiring an interrupt status register.
2. Background of Related Art
FIG. 4 shows a conventional technique for handling interrupt signals 670a, 670b from any of one or more agents 630, 632 (e.g., a microprocessor, microcontroller or digital signal processor (DSP)) to a host 620 (e.g., another microprocessor, microcontroller or DSP).
Conventionally, the interrupt signals 670a, 670b are received by appropriate buffering or interfacing circuitry 661a, 661b, and latched for output in an interrupt status register 660. In the conventional method, the host 620 includes appropriate interface circuitry 661a, 661b and at least one bit reserved in the interrupt status register 660 for each interrupting agent 630, 632. However, more detailed information relating to the cause of the interrupt is generally maintained in a set of registers or in a first-in, first-out type memory element in the agent generating the interrupt. The registers are typically addressable by the host either through an input/output (I/0) address ("I/O mapped") or through a memory address ("memory mapped").
For instance, in an application wherein each agent 630, 632 is handling a plurality of data streams, any one data stream (or any time slot within that data stream) can cause an interrupt. However, conventionally only one interrupt line is provided between the interrupting agent 630 or 632 and the host 620. Additional interrupt lines may complicate the circuitry and interrupt servicing of the host computer 620.
Thus, to gain additional information with respect to an interrupt, when one processor (e.g., host 620) is interrupted by another processor (e.g., agent 630 or 632), the host 620 will typically read its interrupt status register 660 to determine the source of the interrupt and, upon servicing of that interrupt request, read a register or other device in the agent 630 or 632 to determine more information regarding the cause of the interrupt.
After the interrupt is serviced, the host 620 will clear the interrupt request latched in the interrupt status register typically as part of an interrupt service routine (ISR).
In addition to the interrupt status register 660, the host 620 will typically further include an interrupt mask register 667 to programmably mask off unwanted interrupts.
The necessary circuitry such as the interface circuitry 661a, 661b, the interrupt status register 660, and/or the interrupt mask register 667 utilize valuable silicon and complicate the circuitry of a host 620, particularly where an agent 630 and/or 632 may cause an interrupt to the host 620 for any of a multitude of reasons, e.g., sourced from any of a multiple of data streams and/or time slots.
Ideally, particularly in a multiple data stream system, the interrupt status register 660 in a host 620 or other processor would reflect at least minimal information regarding the exact cause of the interrupt to avoid the need for the host 620 to then inquire of the agent 630 or 632 to determine the cause, wasting efficiency in the overall system architecture. For instance, in a multiple data stream environment, information regarding the identification of the stream number causing the interrupt is considered to be important information by the present inventors. However, since all data streams are typically independent, the resulting causes of a single agent's interrupt signal are correspondingly independent, and essential data stream information may not be efficiently encoded into the interrupt status register 660 of the host 620. Moreover, a significant amount of physical area of silicon in the host 620 and in the agents 630, 632 would be required to provide such information in an interrupt signal (e.g., data stream number and interrupt type), particularly as the number of data streams increases.
There is thus a need for an interrupt mechanism and signal which provides a host with suitable information to identify the source of the interrupt. There is also a need to minimize the amount of additional circuitry necessary to implement an informative interrupt mechanism.